1. Field of the Invention
The present invention relates to information processing systems such as personal computers and workstations. More particularly, it relates to techniques for controlling the bus of an information processing system.
2. Description of the Related Art
In an information processing system, a plurality of modules connected to a bus transfer data in synchronism with a common clock. A technique for controlling the synchronous bus is known from, for example, the official gazette of Japanese Patent Application Laid-open No. 11872/1986.
Such a prior-art control of the synchronous bus will be explained.
FIG. 16 of the accompanying drawings illustrates the timings of data transfer on the bus according to the synchronous bus controlling technique in the prior art.
Referring to the figure, symbol CLK denotes a synchronous clock for data transfer, which is common to all modules connected to a bus. Symbol A/D denotes an address and data which are multiplexed together. An address valid signal ADRV indicates that the address of the signal A/D is valid. A signal WRITE serves to designate a write access, and it also indicates that the data of the signal A/D is valid. In addition, a wait signal WAIT serves to notify a master side of the fact that a buffer on a slave side is not in a status capable of accepting the data.
In a case where one of the modules is to access another for a write operation by the use of the bus configured of such signal lines, the bus master first asserts the address valid signal ADRV indicating the validity of the address on the line A/D, and it simultaneously delivers the address of the access destination to the line A/D.
On the other hand, the slave module senses that the write access is directed toward itself, on the basis of the decoded result of the address and the designation signal WRITE for the write access. In a case where the slave module is ready for accepting the data, it accepts the valid data on the line A/D at the timing of the synchronous clock CLK. In contrast, in a case where the slave module is not ready for accepting the data, it requests the prolongation of a data cycle by the use of the wait signal WAIT which notifies the master side that it is incapable of accepting the data.
In a case where the wait signal WAIT is asserted, the master module prolongs the data cycle during the assertion. When the slave module is ready to accept the data, it accepts the valid data on the line A/D at the timing of the synchronous clock CLK, and it negates the wait signal WAIT. Upon the negation of the wait signal WAIT, the master module finishes the data cycle and ends the access.
In this manner, according to the prior-art technique for controlling the synchronous bus, the master module transfers the data to the slave module, and during the report to each other whether or not the data transfer is possible, using the wait signal WAIT in handshake fashion.